Gallium Arsenide (GaAs) – Energy Band Structure In this article, the energy band structure of GaAs is explained with a diagram and also with respect to its comparison with Silicon. The cause of the curves in the valence band and conduction band of GaAs is thoroughly explained. Electron Mobility, a characteristic of GaAs, and its […]

Gallium Arsenide (GaAs) – Channeling Effect This article explains the channeling effect of Gallium Arsenide (GaAs), and its orientation dependency. The concept of axial channeling is also explained. Before going into details, it is better to know the basics on GaAs in VLSI technology. Click on the link below. TAKE A LOOK : ULTRA-FAST SYSTEMS

Gallium Arsenide (GaAs) Doping This article briefly explains the compound semiconductor Gallium Arsenide (GaAs) with a figure showing the arrangement of atoms. The Gallium Arsenide (GaAs) doping process, with respect to the p-type and n-type material is also explained with diagrams. Before going into details, it is better to know the basics on GaAs in

In this post, the origin of Gallium and Arsenic, as well as the structure and properties of the Gallium Arsenide (GaAs) crystal is explained in detail. The atomic structure of Gallium and Arsenic are explained with diagrams and also compared with Silicon. The valence configuration of Ga, As and Si is also shown. Before going

Ultra-fast Systems and GaAs VLSI Technology In this post, we will briefly review some of the limitations of silicon devices and then look at the emerging alternative for ultra-fast systems — gallium arsenide. Submicron CMOS technology Speed and smaller device dimensions are closely interrelated and we have already touched on the fact that the foreseeable

V-Groove MOS (VMOS) This article explains in detail about the structure of VMOS with diagram, its characteristics, anisotropic etching and also the applications of VMOS. To know the basics, click on the links given below. TAKE A LOOK : SHORT CHANNEL MOS STRUCTURES VMOS Structure The structure of VMOS is similar to short-channel power FET

Double-Diffused MOS (DMOS) In this article, the Double-Diffused MOS (DMOS) structure is explained with a diagram. The working of Vertical DMOS Transistor is also explained in detail with its structural analysis and diagram. To know the basics of DMOS take a look at the following posts. TAKE A LOOK : SHORT CHANNEL MOS STRUCTURES The

Short Channel MOS Structures This article discusses the different factors that limit the speed of a MOSFET. The common methods to reduce the parasitics like Scaled MOS (SMOS) and High-performance MOS (HMOS) is explained in detail with their structure and diagram. There are many factors that limit the speed of a MOSFET. Because of the

NMOS Fabrication Process In this article the various steps needed for NMOS Fabrication are explained in detail along with diagrams. To know the basic IC Fabrication Techniques, click on the link below. TAKE A LOOK : IC FABRICATION TECHNIQUES There are a large number and variety of basic fabrication steps used in the production of

PMOS vs NMOS The advantages of n-channel MOSFET’s over p-channel MOSFET’s and vice versa have been explained in detail. Even the problems that NMOS faces in device processing and oxidation have also been explained. n-channel MOSFETs have some inherent performance advantages over p-channel MOSFET’s. The mobility of electrons, which are carriers in the case of

MOSFET Technology and Various MOS Process This article focuses on basics of MOSFET Technology,basics of various MOS process like p-channel MOS (PMOS), n-channel MOS (NMOS), Complimentary MOS (CMOS) – its manufacturing, cross section, and other advantages of one over other. Most of the LSI/VLSI digital memory and microprocessor circuits is based on the MOS Technology.

Dielectric Isolation in Integrated Circuits This article focuses on Dielectric isolation in various Integrated Circuits; especially in the VLSI sector, discusses various methods used for dielectric isolation like V-groove isolation, Silicon on Insulator technology and Epitaxial layer overgrowth. Dielectric isolation, as you all know, is the process of electrically isolating various components in the IC

The figure below shows some IC JFET structures. The n-channel JFET structure of first figure [a] is compatible with the n-p-n transistor fabrication sequence. Another view of this n-channel JFET is shown in second figure [a], where we note that the top p+ gate region extends beyond the n-type epitaxial layer region to make contact

Monolithic Planar Diode Configurations We have seen that in the fabrication of an IC the geometry and the doping of the various layers must be chosen to optimize uncharacteristic of the transistor which is the most important device. It is not economically feasible to provide extra processing steps to fabricate diodes. Therefore diodes are generally

Once all components are fabricated on a single crystal wafer, they must be electrically isolated from each other. The problem is not encountered indiscrete circuits, because physically all components are isolated. There are two methods of isolation in Integrated circuits. They are P-N  junction isolation and Dielectric isolation In this post we shall discuss p-n

In this post, we shall discuss, the fabrication of a standard, junction- isolated bipolar IC.  Of course, many devices can be formed at a time over the surface of the water if appropriate patterns are provided. We shall show only one device, that is, a bipolar transistor as an example. The major steps in the